FPGA-Based 5-Stage Pipelined Processor

May 2025 - August 2025

Built a MIPS-based 5-stage pipelined processor using Verilog HDL within the Xilinx Vivado Design Suite. Performed RTL design, behavioural simulation, synthesis, place-and-route, and deployment on FPGA. Optimised for throughput, minimised pipeline hazards, and verified functionality through comprehensive testbenches and timing-driven verification.

Tech: Verilog HDL, Xilinx Vivado, FPGA, RTL Design, MIPS Architecture, Digital Design